A semiconductor device called “SOC (System On Chip)” is one embodiment of semiconductor devices. In this type of semiconductor device, a plurality of logic circuits, memory cells, and the like are provided on one chip. The following describes a semiconductor device in which an SRAM (Static Random Access Memory) is applied as a memory cell of such a semiconductor device.
The SRAM memory cell includes: a flip flop with two inverters cross-coupled to each other; and two access transistors. In the flip flop, two storage nodes cross-coupled to each other are provided. The two storage nodes are in a bistable state such that one storage node is set to have a high-level potential and the other storage node is set to have a low-level potential. This state is maintained as long as a predetermined power supply potential is applied. The state is stored as “1” or “0” as information.
In a general SRAM memory cell having six transistors, a drive transistor is connected between a storage node and a ground potential, and a load transistor is connected between the storage node and a power supply potential. Further, an access transistor is connected between the storage node and a bit line. Data is written and read via the access transistor.
When reading data, it is required to increase a threshold voltage of the access transistor and attain a high ratio (β ratio) of a current of the drive transistor to a current of the access transistor in order to secure a read margin. On the other hand, when writing data, it is required to decrease the threshold voltage of the access transistor and attain a high ratio (γ ratio) of the current of the access transistor to a current of the load transistor in order to secure a write margin.
As an access transistor satisfying such requirements, there has been proposed an access transistor in which a pair of halo regions have asymmetric impurity concentrations in order to adjust the threshold voltage thereof in an SRAM memory cell described in Non-Patent Document 1 or Non-Patent Document 2. Specifically, the proposed access transistor is configured as follows. Of the pair of halo regions, a halo region connected to a storage node has an impurity concentration higher than the impurity concentration of a halo region connected to a bit line. It should be noted that the term “halo region” refers to an impurity region formed to suppress a short channel effect in a transistor having reduced size. It should be also noted that ion implantation for forming such a halo region is also referred to as “pocket implantation”. Meanwhile, Non-Patent Document 3 has proposed a layout for suppressing fluctuations of a threshold voltage of a transistor included in an SRAM.